The present invention relates to a semiconductor device and a SiP (system in package) using the same. The present invention relates particularly to a semiconductor device having an active element circuit including high breakdown active elements, and a logic circuit operated at a low voltage, both of which are integrated into the same LSI (large scale integrated circuit) chip.
A CMOS-LSI (complementary metal oxide semiconductor LSI) device brings about an improvement in performance and a reduction in power consumption by a scale-down technology. As to the power consumption in particular, the effect of reducing a power supply voltage by scaling is extremely large. LSIs for automobile use, household electrical appliances and industrial applications, however, often need a high power supply voltage used in an interface circuit to the outside. There has been a demand for a high breakdown active element unbroken even by a high power supply voltage, a function for adjusting a difference in power supply voltage between an externally-driven device and an element, and a function for generating a high terminal voltage by a switching operation in an LSI operated at a low power supply voltage. It is general that as the high breakdown active element, an LDMOS (Laterally Diffused MOS) is used to enhance a drain breakdown voltage, or a MOS transistor high in gate breakdown voltage (or thick in gate insulating film thickness) is used. A DC-DC converter is commonly used for voltage adjustments at the time that an external interface circuit and a low voltage-driven LSI are coupled to each other, and generates a voltage of a desired voltage level to the coupling side of a supplied power supply voltage.
A high breakdown LDMOS transistor operated at a high voltage may be integrated into an LSI chip in addition to a MOS transistor operated at a low voltage, such as used in a logic circuit. In a high breakdown MOS transistor as compared with a MOS transistor integrated into a low voltage logic circuit, the distance between its gate and drain is increased to make a drain breakdown voltage high, and further a gate insulating film is formed thick to increase a gate breakdown voltage. Therefore, in order to bring the high breakdown MOS transistor into integration, there is a need to add a process for forming the high breakdown MOS transistor aside from a process for forming the low voltage-operated MOS transistor that configures the low voltage logic circuit. In order to place in mixed form, a high voltage circuit having a low voltage logic circuit and a high breakdown MOS transistor both integrated into the same LSI chip, there is a need to form a high voltage circuit aside from an area of a semiconductor substrate, which is provided with the low voltage logic circuit. This unavoidably leads to an increase in chip area and an increase in process cost.
On the other hand, a DC-DC converter integrated into an LSI is commonly configured using active elements (specifically, a transistor and a diode) formed in a semiconductor substrate. In particular, a recent LSI, however, brings in various problems in that the DC-DC converter is configured by the active elements formed in the semiconductor substrate. Firstly, since a power supply voltage for operating a logic circuit in the process of scaling a signal voltage and a size becomes lower, it has been difficult for the logic circuit and the DC-DC converter to configure using active elements of the same design. Integrating active elements appropriate to their operating voltages into the same semiconductor substrate causes the need for the addition of a complex process and leads to an increase in chip cost.
The second resides in that a semiconductor device in which a DC-DC converter is configured by active elements formed in a semiconductor substrate causes an increase in chip size. In such a configuration that the active elements that configure the DC-DC converter are formed in the semiconductor substrate, there is a need to prepare an area in which the active elements that configure the DC-DC converter are formed, aside from an area in which the active elements that configure the logic circuit are formed. This leads to an increase in chip size, i.e., an increase in chip cost. The active elements that configure the DC-DC converter are large in size because they need the ability to drive large current. Thus, the problem of the increase in chip size can be significant. Further, a high voltage may be applied to the active elements that configure the DC-DC converter. For example, a short-circuit developed between the source and drain of a transistor device, and characteristic degradation due to the injection of electrical charges into a gate insulating film may be caused.
As a technology capable of being related to the present application, Japanese Unexamined Patent Publication No. 2010-141230 has disclosed a technology in which semiconductor layers are formed in a wiring layer and semiconductor elements are formed using the semiconductor layers. As materials for the semiconductor layers, may be mentioned oxide semiconductors such as InGaZnO (IGZO), ZnO, etc., polysilicon and amorphous silicon. As applications for the semiconductor elements provided in the wiring layer, may be mentioned transistors that are switching elements. There has also been disclosed a technology in which each of the semiconductor elements is provided with a trap film and a backgate electrode and used as a memory element. In Japanese Unexamined Patent Publication No. 2010-141230, however, no mention is made to a circuit electrically coupled to a low voltage logic circuit via wirings using active elements that configure the low voltage logic circuit, and a DC-DC converter.
Japanese Unexamined Patent Publication No. 2007-157932 has disclosed that an amorphous semiconductor layer is formed above a semiconductor substrate formed with an integrated circuit, and an external interface circuit operated at a higher voltage than at the integrated circuit is mounted in the amorphous semiconductor layer. Incidentally, the definition of an “external interface circuit” is not shown in this publication. A circuitry coupling between an integrated circuit formed using a silicon substrate and a high voltage operation circuit located above is not definite.